cdc 3272g may/2005 product information cdc 3272g arm7-based car dashboard controller the cdc 3272g-cx is a pin-compatible mask rom derivative of micronas? 32-bit car dashboard controller family based on an arm7tdmi cpu core (cdc 32xxg). this device comes along with additional features of the cx platform like a superior power saving module (psm) and two high- speed can module (bosch v2.0b). main characteristics of the psm are three addi- tional low-power modes (idle, wake, and standby), an internal rc oscillator, a poll- ing/flash timer output, as well as an rtc (real time clock). the cdc 3272g also contains the patented built-in erm (emi reduction module). features 384 kb mask rom 16 kb sram four cpu operation modes (deep slow, slow, fast, pll) three low-power modes (idle, wake, standby) rtc delivering hours, minutes, seconds polling/flash timer output pll circuitry delivering up to 50 mhz 4- to 5-mhz oscillator emi reduction module (erm) digital watchdog central clock divider interrupt controller with 40 inputs and 16 priority levels six port interrupts regulator input supervision for reset/ alarm (alarm comparator) clock and supply supervision 16-channel 10-bit adc two comparators adc reference (1 internal, 3 external) 48 4 lcd module three dma channels two uarts, two spis digitbus master module two can modules with 512 bytes each of object ram according to bosch speci- fication v2.0b (32 message objects) two i 2 c master modules seven stepper motor drivers six pwm modules (configurable as 2 8 bit or 1 16 bit) pulse frequency modulator sound generator with auto decay two sw-selectable clock outputs 16-bit free-running counter with six cap- ture/compare modules 1 16-bit timer and 4 8-bit timer patch module (up to 10 cells) jtag interface ? 40 to +105 c case temperature range single 3.5 v to 5.5 v supply voltage (limited i/o performance below 4.5 v) up to 102 gpios 128-pin pqfp package, 0.5 mm pin pitch
product information cdc 3272g may/2005 all information and data contained in this product information are without any commitment, are not to be consid- ered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. product or development sample availability and delivery are exclusively subject to our respective order confirmation form. by this publication, micronas gmbh does not assume responsibility for patent infringements or other rights of third parties which may result from its use. micronas gmbh ? hans-bunte-strasse 19 ? d-79108 freiburg (germany) ? p.o. box 840 ? d-79008 freiburg (germany) tel. +49-761-517-0 ? fax +49-761-517-2174 ? e-mail: docservice@micronas.com ? www.micronas.com no part of this publication may be reproduced, photo- copied, stored on a retrieval system, or transmitted without the express written consent of micronas gmbh. edition may 18, 2005; order no. 6251-615-1pi jtag probe evb jtag jtag etm trace probe logic analyzer development tools evaluation chip cdc 3205g featuring ? etm via embedded emulation jtag ? rom/flash emulation with external sram (up to 8 mbytes) evaluation board (evb) including the cdc 3205g for evaluation and debug- ging of embedded systems application board (apb) for flash mem- ory programming probe for pqfp128 software environment (compiler, linker, assembler) from 3 rd party vendors rtos from 3 rd party vendors can protocol stacks system architecture the car dashboard controller cdc 3272g contains an embedded arm7tdmi proces- sor which operates at a maximum clock fre- quency of 50 mhz. the internal high-speed bus connects the following peripherals to the arm7tdmi pro- cessor: icu (interrupt control unit) sram dma the 16/32-bit bus connects to the mask rom. all other peripherals are connected to the i/o bus. all i/o ports have multiple func- tions to obtain utmost flexibility. a total of 102 gpios can be selected. the built-in erm delivers superb emi results reducing the peak values by up to 10 db v. the cdc 3272g is fully pin- and software- compatible with all other members of the cdc 32xxg family. fig. 2: block diagram of the cdc 3272g vrefint vref avdd avss bvdd hports uports pports uarts 2 uart uarts 2 spi uarts 2 can uarts digitbus uarts 2 i2c bus uarts lcd control uarts audio module uarts clock out 0,1 uarts 16- bit ccc 0 uarts uarts 16- bit ccc 1 uarts arm7tdmi cpu dma contr. 40-input interrupt controller 16 kb sram patch module bridge bridge bus controller p0.6 comp wait comp vdd vss uvdd uvss 2.5-v reg. 2.5-v reg. 7 stepper motor module uarts 1 16-bit timer uarts 4 8-bit timer uarts 6 8/16-bit pwm 18 52 32 capcom 0,1,2,3 capcom 4, 5 pfm0/1 384 kb rom jtag interface test / debug reset test watchdog clock pll/erm rtc power saving 10-bit adc bandgap ref. fig. 1: development tool setup
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